#ifndef __PLATFORM_QM102V__
#define __PLATFORM_QM102V__

#define RAM_BASE			(0x1C200000)
#define DDR_BASE			(0x40000000)
#define GICD_REG_BASE		(GIC_REG_BASE+0x1000)
#define GICC_REG_BASE		(GIC_REG_BASE+0x2000)

#define GIC_REG_BASE			(0x00200000)
#define CPU_SYS_APB_REG_BASE	(0x0c000000)
#define DMA0_REG_BASE			(0x0C700000)
#define C2C_INTR0_REG_BASE		(0x0A100000)
#define C2C_INTR1_REG_BASE		(0x0A200000)
#define UART0_REG_BASE			(0x08f00000)
#define UART1_REG_BASE			(0x09000000)
#define UART2_REG_BASE			(0x09100000)
#define SPI0_REG_BASE			(0x08c00000)
#define I2C0_REG_BASE			(0x08d00000)
#define I2C1_REG_BASE			(0x08e00000)
#define I2S_REG_BASE			(0x08900000)
#define TOP_PRE_DIV_RF_REG_BASE	(0x10300000)
#define TOP_CLK_RF_REG_BASE		(0x10300200)
#define TOP_CLK_GATE_RF_REG_BASE (0x10300400)
#define TIMER0_REG_BASE			(0x09800000)
#define SYS_TIMER_REG_BASE		(0x09700000)
#define RTC_REG_BASE			(0x2c900000)
#define WDT_REG_BASE			(0x09600000)
#define GPIO0_REG_BASE			(0x0B000000)
#define GPIO1_REG_BASE			(0x0B010000)
#define GPIO2_REG_BASE			(0x0B020000)
#define GPIO3_REG_BASE			(0x0B030000)
#define GPIO4_REG_BASE			(0x0B040000)
#define GPIO5_REG_BASE			(0x0B050000)
#define SPI1_REG_BASE			(0x08b00000)
#define PWM_REG_BASE			(0x09500000)
#define CEN_GLB_APB_REG_BASE	(0x10000000)
#define CEN_PIN_REG_BASE		(0x10200000)
#define GMAC0_REG_BASE			(0x1c600000)
#define SADC_REG_BASE			(0x1c500000)
#define REG_EPHY_BASE           (0x1C900000)
#define EFUSE_REG_BASE			(0x0A700000)
#define AES_REG_BASE			(0x0C600000)
#define SDC1_REG_BASE			(0x2D200000)
#define DMC_SYS_APB_REG_BASE	(0x24000000)
#define SDC0_REG_BASE			(0x2D100000)
#define USB2_REG_BASE			(0x1d100000)
#define PTS_REG_BASE			(0x2c300000)
#define VEU_SYS_APB_REG			(0x1c000000)


#define VEU_SYS_PIN_REG_BASE	(0x1c100000)
#define ISP_SYS_PIN_REG_BASE	(0x2c000000)
#define CSI_SYS_PIN_REG_BASE	(0x2c600000)
#define CPU_SYS_PIN_REG_BASE	(0x0b100000)
#define CPU_SYS_CLK_RF_BASE     (0x09200200)

#define REG_PMU_CHIP_ID			(CEN_GLB_APB_REG_BASE + 0x0198)
#define REG_PMU_BOOT_MODE		(CEN_GLB_APB_REG_BASE + 0x0508)
#define REG_PMU_DDR_SIZE		(CEN_GLB_APB_REG_BASE + 0x050C)
#define REG_PMU_CHIP_INFO		(CEN_GLB_APB_REG_BASE + 0x0514)
#define REG_PMU_EPHY_PARAM		(CEN_GLB_APB_REG_BASE + 0x0518)
#define REG_PMU_RTC_PARAM		(CEN_GLB_APB_REG_BASE + 0x051C)

#define REG_GLB_RESET			(CEN_GLB_APB_REG_BASE+0x100)
#define SW_GLB_RST					(BIT(0))
#define SW_EXT_RST					(BIT(1))

#define REG_WR_PROTECT			(CEN_GLB_APB_REG_BASE+0x548)

#define UART_CLOCK_FREQ			24000000    //24M

/*VDU_SYS_APB_REG_BASE + offset ctl efuse cmp func*/

#define DMC_CLK_CTRL (DMC_SYS_APB_REG_BASE+0x300)

#define CEN_PERI_APB_CLK_CTRL (CPU_SYS_APB_REG_BASE+0xb0) 
#define AP_MTX_CLK_CTRL0 (CPU_SYS_APB_REG_BASE+0xdc)
#define AP_EPHY_CTRL0 (CPU_SYS_APB_REG_BASE + 0x1fc)
#define AP_GMAC_CTRL0 (CPU_SYS_APB_REG_BASE + 0x1dc)


#define VEU_SYS_CLK_CFG1 (VEU_SYS_APB_REG+0x10)
#define VEU_SYS_CLK_CFG2 (VEU_SYS_APB_REG+0x14)
#define CKG_SPIC_CFG     (CPU_SYS_CLK_RF_BASE + 0x6c)

enum DMA_HW_HS_MAP
{
    UART0_RX,
    UART0_TX,
    UART1_RX,
    UART1_TX,
    I2C0_RX,
    I2C0_TX,
    I2C1_RX,
    I2C1_TX,
    AES_RX,
    AES_TX,
    SPI1_RX,
    SPI1_TX,
    SPI0_RX,
    SPI0_TX,
    ACODEC_TX,
    ACODEC_RX,
    I2S0_RX,
    I2S0_TX,
    DMA_HW_HS_END,
 };


struct s_train_val{
	unsigned char *name;
	unsigned int src_add;
	unsigned int src_mask;
	unsigned int src_vaild_index;
	unsigned char *dst_base_name;
	unsigned int dst_add;
	unsigned int dst_vaild_index;
	unsigned int *bind_train_array;
	unsigned int bind_train_size;
	int usr_train_offset;
};

struct gmac_plat_info{
	unsigned int regs;
	unsigned int id;
#define MAX_PHY_DRIVER_SUPPORT_SIZE	5
	char *phy_driver_list[MAX_PHY_DRIVER_SUPPORT_SIZE];
    void *p_cfg_array;
};





struct mshc_lite_emmc_card_info{

	char *mmc_name;
    char mmc_name_buf[16];
    #define FORCE_USR_SETTING   0x55aaaa55
    //default auto..
    #define AUTO_TUNING_THEN_REC  0x0
    unsigned int flag;
    #define AUTO_TUNING_DONE    0x656e6f64  //means 'done'
    unsigned int magic;
    //cpy sw para to emmc mem..
    unsigned int sup_mode;

    unsigned int es_sup;

    unsigned int hs_tx_data;
    unsigned int hs_rx_cmd;
    unsigned int hs_rx_data;

    unsigned int hs200_tx_data;
    unsigned int hs200_rx_cmd;
    unsigned int hs200_rx_data;

    unsigned int hs400_tx_data;
    unsigned int hs400_rx_cmd;
    unsigned int hs400_rx_data;
};

struct mshc_lite_plat_info{

	unsigned int id;
    char *name;
   	unsigned int ctrl_regs;
    unsigned int phy_regs;
    struct mshc_lite_emmc_card_info *emmc_info_list;
    //phy init
    void (*soc_clk_init)(void *p_rev);
    //void (*phy_init)(void *p_rev);
    void (*soc_ctrl_reset)(void *p_rev);
    void (*clk_set)(void *p_rev,unsigned int clk);
};



#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400
#define FH_GMAC_PHY_INTERNAL_V2 0x46480000
#define FH_GMAC_PHY_RTL8211F 0x001cc916
#define FH_GMAC_PHY_MAE0621 0x7b744411
#define FH_GMAC_PHY_JL2101 0x937c4032
#define FH_GMAC_PHY_DUMMY	0xE3FFE3FF
#endif
